Bài giảng Thiết kế logic số (VLSI design): Chương 4.3 - Trịnh Quang Kiên

Bài giảng Thiết kế logic số (VLSI design): Chương 4.3 trình bày về quy trình thiết kế trên FPGA và một số nội dung như: VHDL and Schematic, Synthesis, Synthesis - netlist, Synthesis – Technology Schematic,... Mời các bạn cùng tham khảo.
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Bài giảng Thiết kế logic số (VLSI design): Chương 4.3 - Trịnh Quang KiênThiếtkếlogicsố (VLSIdesign) BộmônKTXung,số,VXL 06/2010 QuytrìnhthiếtkếtrênFPGAISE (Intergrated Software Enviroment) QuytrìnhthiếtkếtrênFPGADesignandimplementasimpleunitpermittingto Specification (Lab Experiments)speedupencryptionwithRC5similarcipherwithfixedkeyseton8031microcontroller.Unlikeintheexperiment5,thistimeyourunithastobeabletoperformanencryptionalgorithmbyitself,executing32rounds….. VHDL description (Your Source Files)LibraryIEEE;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entityRC5_coreis Functional simulationport(clock,reset,encr_decr:instd_logic;data_input:instd_logic_vector(31downto0);data_output:outstd_logic_vector(31downto0);out_full:instd_logic;key_input:instd_logic_vector(31downto0);key_read:outstd_logic;);endAES_core; Synthesis Post-synthesis simulation QuytrìnhthiếtkếtrênFPGAImplementation Timing simulationConfiguration On chip testing VHDLandSchematic library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity compare_module is Port (value : in std_logic_vector (3 downto 0); res : out std_logic); end compare_module; architecture Behavioral of compare_module is signal std : std_logic_vector (4 downto 0); begin val Synthesis Synthesis UNISIMLibrarylibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;entity compare_module isPort (value : in std_logic_vector (3 downto 0); res : out std_logic);end compare_module;architecture Behavioral of compare_module issignal std : std_logic_vector (4 downto 0);beginval Synthesisnetlistlibrary IEEE;library IEEE;use IEEE.STD_LOGIC_1164.ALL;library UNISIM;use UNISIM.VCOMPONENTS.ALL;use UNISIM.VPKG.ALL;entity sp3_led is port ( LED1 : out STD_LOGIC; LED2 : out STD_LOGIC;...);end sp3_led;architecture Structure of sp3_led issignal SW8_IBUF_31 : STD_LOGIC;begin LED81 : LUT2 generic map( INIT => X1 ) port map ( I0 => SW8_IBUF_31, I1 => SW7_IBUF_29, O => LED8_OBUF_15 );...Synthesis–TechnologySchematicSynthesis–RTLSchematic Synthesis–UCFfile# IO location definationNET HIGH_voltage LOC = P102;NET LOW_voltage LOC = P100;NET voltage[0] LOC = P160;NET voltage[1] LOC = P161;NET voltage[2] LOC = P162;NET voltage[3] LOC = P163;# Timing constraintINST LOW_voltage TNM = OUT_REG;INST HIGH_voltage TNM = OUT_REG;NET voltage[0] OFFSET = IN 2 ns VALID 0.5 ns BEFORE CLK TIMEGRPOUT_REG RISING;NET voltage[1] OFFSET = IN 2 ns VALID 0.5 ns BEFORE CLK TIMEGRPOUT_REG RISING;NET voltage[2] OFFSET = IN 2 ns VALID 0.5 ns BEFORE CLK TIMEGRPOUT_REG RISING;NET voltage[3] OFFSET = IN 2 ns VALID 0.5 ns BEFORE CLK TIMEGRPOUT_REG RISING;Implementation Translate Synthesis Circuit netlist Timing Constraints Constraint Editor Electronic Design NativeInterchange Format Constraint File EDIF NCF UCF User Constraint File Translation NGD Native Generic Database fileMappingChươngIIIFPGA Place&RouteFPGAVerification Giaothứctruyềntinnốitiếp IDLE START DATA PARITY STOP IDLE RX TbraudBit counter x 0 0 1 2 3 4 5 6 7 8 0 ...