Basic Concepts part 1

[ Team LiB ] 3.1 Lexical Conventions The basic lexical conventions used by Verilog HDL are similar to those in the C programming language. Verilog contains a stream of tokens. Tokens can be comments, delimiters, numbers, strings, identifiers, and keywords.
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Basic Concepts part 1[ Team LiB ]3.1 Lexical ConventionsThe basic lexical conventions used by Verilog HDL are similar to those in the Cprogramming language. Verilog contains a stream of tokens. Tokens can be comments,delimiters, numbers, strings, identifiers, and keywords. Verilog HDL is a case-sensitivelanguage. All keywords are in lowercase.3.1.1 WhitespaceBlank spaces () , tabs ( ) and newlines ( ) comprise the whitespace. Whitespace isignored by Verilog except when it separates tokens. Whitespace is not ignored in strings.3.1.2 CommentsComments can be inserted in the code for readability and documentation. There are twoways to write comments. A one-line comment starts with //. Verilog skips from thatpoint to the end of line. A multiple-line comment starts with /* and ends with */.Multiple-line comments cannot be nested. However, one-line comments can beembedded in multiple-line comments.a = b && c; // This is a one-line comment/* This is a multiple line comment *//* This is /* an illegal */ comment *//* This is //a legal comment */3.1.3 OperatorsOperators are of three types: unary, binary, and ternary. Unary operators precede theoperand. Binary operators appear between two operands. Ternary operators have twoseparate operators that separate three operands.a = ~ b; // ~ is a unary operator. b is the operanda = b && c; // && is a binary operator. b and c are operandsa = b ? c : d; // ?: is a ternary operator. b, c and d are operands3.1.4 Number SpecificationThere are two types of number specification in Verilog: sized and unsized.Sized numbersSized numbers are represented as . is written only in decimal and specifies the number of bits in the number. Legalbase formats are decimal (d or D), hexadecimal (h or H), binary (b or B) and octal (oor O). The number is specified as consecutive digits from 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, a, b,c, d, e, f. Only a subset of these digits is legal for a particular base. Uppercase letters arelegal for number specification.4b1111 // This is a 4-bit binary number12habc // This is a 12-bit hexadecimal number16d255 // This is a 16-bit decimal number.Unsized numbersNumbers that are specified without a specification are decimal numbersby default. Numbers that are written without a specification have a default numberof bits that is simulator- and machine-specific (must be at least 32).23456 // This is a 32-bit decimal number by defaulthc3 // This is a 32-bit hexadecimal numbero21 // This is a 32-bit octal numberX or Z valuesVerilog has two symbols for unknown and high impedance values. These values are veryimportant for modeling real circuits. An unknown value is denoted by an x. A highimpedance value is denoted by z.12h13x // This is a 12-bit hex number; 4 least significant bits unknown6hx // This is a 6-bit hex number32bz // This is a 32-bit high impedance numberAn x or z sets four bits for a number in the hexadecimal base, three bits for a number inthe octal base, and one bit for a number in the binary base. If the most significant bit of anumber is 0, x, or z, the number is automatically extended to fill the most significant bits,respectively, with 0, x, or z. This makes it easy to assign x or z to whole vector. If themost significant digit is 1, then it is also zero extended.Negative numbersNegative numbers can be specified by putting a minus sign before the size for a constantnumber. Size constants are always positive. It is illegal to have a minus sign between and . An optional signed specifier can be added for signedarithmetic.-6d3 // 8-bit negative number stored as 2s complement of 3-6sd3 // Used for performing signed integer math4d-2 // Illegal specificationUnderscore characters and question marksAn underscore character _ is allowed anywhere in a number except the first character.Underscore characters are allowed only to improve readability of numbers and areignored by Verilog.A question mark ? is the Verilog HDL alternative for z in the context of numbers. The ?is used to enhance readability in the casex and casez statements discussed in Chapter 7,where the high impedance value is a dont care condition. (Note that ? has a differentmeaning in the context of user-defined primitives, which are discussed in Chapter 12,User-Defined Primitives.)12b1111_0000_1010 // Use of underline characters for readability4b10?? // Equivalent of a 4b10zz3.1.5 StringsA string is a sequence of characters that are enclosed by double quotes. The restriction ona string is that it must be contained on a single line, that is, without a carriage return. Itcannot be on multiple lines. Strings are treated as a sequence of one-byte ASCII values.Hello Verilog World // is a stringa / b // is a string3.1.6 Identifiers and KeywordsKeywords are special identifiers reserved to define the language constructs. Keyword ...