Overview Of Degital Design With Verilog HDL part 2

[ Team LiB ] 1.2 Emergence of HDLs For a long time, programming languages such as FORTRAN, Pascal, and C were being used to describe computer programs that were sequential in nature. Similarly, in the digital design field, designers felt the need for a standard language
Nội dung trích xuất từ tài liệu:
Overview Of Degital Design With Verilog HDL part 2[ Team LiB ]1.2 Emergence of HDLsFor a long time, programming languages such as FORTRAN, Pascal, and C were beingused to describe computer programs that were sequential in nature. Similarly, in thedigital design field, designers felt the need for a standard language to describe digitalcircuits. Thus, Hardware Description Languages (HDLs) came into existence. HDLsallowed the designers to model the concurrency of processes found in hardware elements.Hardware description languages such as Verilog HDL and VHDL became popular.Verilog HDL originated in 1983 at Gateway Design Automation. Later, VHDL wasdeveloped under contract from DARPA. Both Verilog® and VHDL simulators to simulatelarge digital circuits quickly gained acceptance from designers.Even though HDLs were popular for logic verification, designers had to manuallytranslate the HDL-based design into a schematic circuit with interconnections betweengates. The advent of logic synthesis in the late 1980s changed the design methodologyradically. Digital circuits could be described at a register transfer level (RTL) by use ofan HDL. Thus, the designer had to specify how the data flows between registers and howthe design processes the data. The details of gates and their interconnections toimplement the circuit were automatically extracted by logic synthesis tools from the RTLdescription.Thus, logic synthesis pushed the HDLs into the forefront of digital design. Designers nolonger had to manually place gates to build digital circuits. They could describe complexcircuits at an abstract level in terms of functionality and data flow by designing thosecircuits in HDLs. Logic synthesis tools would implement the specified functionality interms of gates and gate interconnections.HDLs also began to be used for system-level design. HDLs were used for simulation ofsystem boards, interconnect buses, FPGAs (Field Programmable Gate Arrays), and PALs(Programmable Array Logic). A common approach is to design each IC chip, using anHDL, and then verify system functionality via simulation.Today, Verilog HDL is an accepted IEEE standard. In 1995, the original standard IEEE1364-1995 was approved. IEEE 1364-2001 is the latest Verilog HDL standard that madesignificant improvements to the original standard.[ Team LiB ][ Team LiB ]1.3 Typical Design FlowA typical design flow for designing VLSI IC circuits is shown in Figure 1-1. Unshadedblocks show the level of design representation; shaded blocks show processes in thedesign flow. Figure 1-1. Typical Design FlowThe design flow shown in Figure 1-1 is typically used by designers who use HDLs. Inany design, specifications are written first. Specifications describe abstractly thefunctionality, interface, and overall architecture of the digital circuit to be designed. Atthis point, the architects do not need to think about how they will implement this circuit.A behavioral description is then created to analyze the design in terms of functionality,performance, compliance to standards, and other high-level issues. Behavioraldescriptions are often written with HDLs.[2][2] New EDA tools have emerged to simulate behavioral descriptions of circuits. Thesetools combine the powerful concepts from HDLs and object oriented languages such asC++. These tools can be used instead of writing behavioral descriptions in Verilog HDL.The behavioral description is manually converted to an RTL description in an HDL. Thedesigner has to describe the data flow that will implement the desired digital circuit.From this point onward, the design process is done with the assistance of EDA tools.Logic synthesis tools convert the RTL description to a gate-level netlist. A gate-levelnetlist is a description of the circuit in terms of gates and connections between them.Logic synthesis tools ensure that the gate-level netlist meets timing, area, and powerspecifications. The gate-level netlist is input to an Automatic Place and Route tool, whichcreates a layout. The layout is verified and then fabricated on a chip.Thus, most digital design activity is concentrated on manually optimizing the RTLdescription of the circuit. After the RTL description is frozen, EDA tools are available toassist the designer in further processes. Designing at the RTL level has shrunk the designcycle times from years to a few months. It is also possible to do many design iterations ina short period of time.Behavioral synthesis tools have begun to emerge recently. These tools can create RTLdescriptions from a behavioral or algorithmic description of the circuit. As these toolsmature, digital circuit design will become similar to high-level computer programming.Designers will simply implement the algorithm in an HDL at a very abstract level. EDAtools will help the designer convert the behavioral description to a final IC chip.It is important to note that, although EDA tools are available to automate the processesand cut design cycle times, the designer is still the person who controls how the tool willperform. EDA tools are also susceptible to the GIGO : Garbage In Garbage Outphenomenon. If used improperly, EDA tools will lead to inefficient designs. Thus, thedesigner still needs to understand the nuances of design methodologies, using EDA toolsto obtain an optimized design.[ Team LiB ][ Team LiB ]1.4 Importance of HDLsHDLs have many advantages compared to traditional schematic-based design. • Designs can be described at a very abstract level by use of HDLs. Designers can write their RTL description without choosing a specific fabrication technology. Logic synthesis tools can automatically convert the design to any fabrication technology. If a new technology emerges, designers do not need to redesign their circuit. ...