Thermal distribution and reliability prediction for 3D Networks-on-chip

In this work, we have investigated the impact of the thermal dissipation difficulty of Network on Chip based 3D-ICs by proposing a method to predict the temperature and MTTF of each region of the targeted system.
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Thermal distribution and reliability prediction for 3D Networks-on-chip VNU Journal of Science: Comp. Science & Com. Eng, Vol. 36, No. 1 (2020) 65-77 Original Article Thermal Distribution and Reliability Prediction for 3D Networks-on-Chip Khanh N. Dang1,*, Akram Ben Ahmed2, Abderazek Ben Abdallah3, Xuan-Tu Tran1 1 VNU University of Engineering and Technology, Vietnam National University, Hanoi, 144 Xuan Thuy, Cau Giay, Hanoi, Vietnam 2 National Institute of Advanced Industrial Science and Technology (AIST), Tsukuba, 305-8568, Japan 3 University of Aizu, Aizu-Wakamatsu, Japan Received 02 April 2020 Revised 02 June 2020; Accepted 06 June 2020 Abstract: As one of the most promising technologies to reduce footprint, power consumption and wire latency, Three Dimensional Integrated Circuits (3D-ICs) is considered as the near future for VLSI system. Combining with the Network-on-Chip infrastructure to obtain 3D Networks-on- Chip (3D-NoCs), the new on-chip communication paradigm brings several advantages. However, thermal dissipation is one of the most critical challenges for 3D-ICs, where the heat cannot easily transfer through several layers of silicon. Consequently, the high-temperature area also confronts the reliability threat as the Mean Time to Failure (MTTF) decreases exponentially with the operating temperature as in Black’s model. Apparently, 3D-NoCs and 3D ICs must tackle this fundamental problem in order to be widely used. However, the thermal analyses usually require complicated simulation and might cost an enormous execution time. As a closed-loop design flow, designers may take several times to optimize their designs which significantly increase the thermal analyzing time. Furthermore, reliability prediction also requires both completed design and thermal prediction, and designer can use the result as a feedback for their optimization. As we can observe two big gaps in the design flow, it is difficult to obtain both of them which put 3D-NoCs under thermal throttling and reliability threats. Therefore, in this work, we investigate the thermal distribution and reliability prediction of 3D-NoCs. We first propose a new method to help simulate the temperature (both steady and transient) using traffic values from realistic and synthetic benchmarks and the power consumption from standard VLSI design flow. Then, based on the proposed method, we further predict the relative reliability between different parts of the network. Experimental results show that the method has an extremely fast execution time in comparison to the acceleration lifetime test. Furthermore, we compare the thermal behavior and reliability between Monolithic design and TSV (Through-Silicon-Via) based design. We also explore the ability to implement the thermal via a mechanism to help reduce the operating temperature. Keywords: Thermal dissipation, Reliability, Through-Silicon-Via, 3D-ICs, 3D-NoCs.* _______ * Corresponding author. E-mail address: khanh.n.dang@vnu.edu.vn https://doi.org/10.25073/2588-1086/vnucsce.245 65 66 K.N. Dang et al. / VNU Journal of Science: Comp. Science & Com. Eng., Vol. 36, No. 1 (2020) 65-77 1. Introduction like to note that the activation energy of Copper is much higher than CMOS material which 3D Networks-on-Chip (3D-NoCs), as a makes TSV more vulnerable than the normal result of combining Networks-on-Chip (NoCs) gates. Since TSV can act as a cooling device, [1] with 3D Integrated Circuit (3D-ICs) [2], is TSV-based NoC has a lower operating considered as one the most promising temperature than Monolithic; however, TSV technologies for IC design [3]. By providing also has lower reliability. Therefore, the parallelism and scalability of the NoCs to 3D- reliability differences between Monolithic and ICs, we even obtain lower power consumption, TSV-based 3D-ICs need to be investigated. shorter wire length while reducing the design While the thermal behavior could be area cost by several times. Among several extracted by performing the real-chip, reliability 3D-ICs, Through-Silicon-Via which constitutes cannot be directly measured. Most industrial as inter-layer wire is one of the near-future methods are based on Black’s model [9] in technologies. Monolithic 3D ICs is another Equation 1 by baking the chip under high method to implement the 3D-ICs [4, 5]. With temperature to accelerate the failure [10-12]. both technologies, we expect to have multiple In this work, we have investigated the layers of the system. To support communication impact of the thermal dissipation difficulty of within the system, 3D-NoCs offer a router- Network on Chip based 3D-ICs by proposing a based infrastructure where the 3D mesh method to predict the temperature and MTTF of topology is used. each region of the targeted system. We first use Despite several advantages, 3D-ICs a ...