Verilog Programming part 29

Time Scales Often, in a single simulation, delay values in one module need to be defined by using certain time unit, e.g., 1 µs, and delay values
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Verilog Programming part 299.4 Time ScalesOften, in a single simulation, delay values in one module need to be defined byusing certain time unit, e.g., 1 µs, and delay values in another module need to bedefined by using a different time unit, e.g. 100 ns. Verilog HDL allows thereference time unit for modules to be specified with the `timescale compilerdirective.Usage: `timescale / The specifies the unit of measurement for times and delays.The specifies the precision to which the delays are rounded offduring simulation. Only 1, 10, and 100 are valid integers for specifying time unitand time precision. Consider the two modules, dummy1 and dummy2, in Example9-8.Example 9-8 Time Scales//Define a time scale for the module dummy1//Reference time unit is 100 nanoseconds and precision is 1 ns`timescale 100 ns / 1 nsmodule dummy1;reg toggle;//initialize toggleinitial toggle = 1b0;//Flip the toggle register every 5 time units//In this module 5 time units = 500 ns = .5 salways #5 begin toggle = ~toggle; $display(%d , In %m toggle = %b , $time, toggle); endendmodule//Define a time scale for the module dummy2//Reference time unit is 1 microsecond and precision is 10 ns`timescale 1 us / 10 nsmodule dummy2;reg toggle;//initialize toggleinitial toggle = 1b0;//Flip the toggle register every 5 time units//In this module 5 time units = 5 s = 5000 nsalways #5 begin toggle = ~toggle; $display(%d , In %m toggle = %b , $time, toggle); endendmoduleThe two modules dummy1 and dummy2 are identical in all respects, except thatthe time unit for dummy1 is 100 ns and the time unit for dummy2 is 1 µs. Thus the$display statement in dummy1 will be executed 10 times for each $displayexecuted in dummy2. The $time task reports the simulation time in terms of thereference time unit for the module in which it is invoked. The first few $displaystatements are shown in the simulation output below to illustrate the effect of the`timescale directive. 5 , In dummy1 toggle = 1 10 , In dummy1 toggle = 0 15 , In dummy1 toggle = 1 20 , In dummy1 toggle = 0 25 , In dummy1 toggle = 1 30 , In dummy1 toggle = 0 35 , In dummy1 toggle = 1 40 , In dummy1 toggle = 0 45 , In dummy1 toggle = 1--> 5 , In dummy2 toggle = 1 50 , In dummy1 toggle = 0 55 , In dummy1 toggle = 1Notice that the $display statement in dummy2 executes once for every ten $displaystatements in dummy1.[ Team LiB ][ Team LiB ]9.5 Useful System TasksIn this section, we discuss the system tasks that are useful for a variety of purposesin Verilog. We discuss system tasks [1] for file output, displaying hierarchy,strobing, random number generation, memory initialization, and value changedump.[1] Other system tasks such as $signed and $unsigned used for sign conversion arenot discussed in this book. For details, please refer to the IEEE Standard VerilogHardware Description Language document.9.5.1 File OutputOutput from Verilog normally goes to the standard output and the file verilog.log.It is possible to redirect the output of Verilog to a chosen file.Opening a fileA file can be opened with the system task $fopen.Usage: $fopen(); [2][2] The IEEE Standard Verilog Hardware Description Language documentprovides additional capabilities for $fopen. The $fopen syntax mentioned in thisbook is adequate for most purposes. However, if you need additional capabilities,please refer to the IEEE Standard Verilog Hardware Description Languagedocument.Usage: = $fopen();The task $fopen returns a 32-bit value called a multichannel descriptor.[3] Only onebit is set in a multichannel descriptor. The standard output has a multichanneldescriptor with the least significant bit (bit 0) set. Standard output is also calledchannel 0. The standard output is always open. Each successive call to $fopenopens a new channel and returns a 32-bit descriptor with bit 1 set, bit 2 set, and soon, up to bit 30 set. Bit 31 is reserved. The channel number corresponds to theindividual bit set in the multichannel descriptor. Example 9-9 illustrates the use offile descriptors.[3] The IEEE Standard Verilog Hardware Description Language documentprovides a method for opening up to 230 files by using a single-channel filedescriptor. Please refer to it for details.Example 9-9 File Descriptors//Multichannel descriptorinteger handle1, handle2, handle3; //integers are 32-bit values//standard output is open; descriptor = 32h0000_0001 (bit 0 set)initialbegin handle1 = $fopen(file1.out); //handle1 = 32h0000_0002 (bit 1 set) handle2 = $fopen(file2.out); //handle2 = 32h0000_0004 (bit 2 set) handle3 = $fopen(file3.out); //handle3 = 32h0000_0008 (bit 3 set)endThe advantage of multichannel descriptors is that it is possible to selectively writeto multiple files at the same time. This is explained below in greater detail.Writing to filesThe system tasks $fdisplay, $fmonitor, $fwrite, and $fstrobe are used to write tofiles.[4] Note that these tasks are similar in syntax to regular system tasks $display,$monitor, etc., but they provide the additional capability of writing to files.[4] The IEEE Standard Verilog Hardware Description Language documentprovides many additional capabilities for file output. The file output system tasksmentioned in this book are adequate for most digital designers. However, if youneed additional capabilities for file output, please refer to the IEEE StandardVerilog Hardware Description Language document.Systems tasks for reading files are also provided by the IEEE Standard VerilogHardware Description Language. These system tasks include $fgetc, $ungetc,$fgetc, $fscanf, $sscanf, $fread, $ftell, $fseek, $rewind, and $fflush. However,most digital designers do not need these capabilities frequen ...